The present invention relates generally to semiconductor device manufacturing processes and, more particularly, to a structure and method of reducing electromigration cracking and extrusion effects in semiconductor devices.
Integrated circuits are typically fabricated with multiple levels of patterned metallization lines, electrically separated from one another by interlayer dielectrics containing vias at selected locations to provide electrical connections between levels of the patterned metallization lines. As these integrated circuits are scaled to smaller dimensions in a continual effort to provide increased density and performance (e.g., by increasing device speed and providing greater circuit functionality within a given area chip), the interconnect linewidth dimension becomes increasingly narrow, which in turn renders them more susceptible to deleterious effects such as electromigration.
Electromigration is a term referring to the phenomenon of mass transport of metallic atoms (e.g., copper or aluminum) which make up the interconnect material, as a result of unidirectional or DC electrical current conduction therethrough. More specifically, the electron current collides with the metal ions, thereby pushing them in the direction of current travel. Over an extended period of time, the accumulation of metal at the anode end of the interconnect material significantly increases the local mechanical stress in the system. This in turn may lead to delamination, cracking, and even metal extrusion from the metal wire, thereby causing an electrical short to adjacent interconnects. Electromigration becomes increasingly more significant in integrated circuit design, as relative current densities through metallization lines continue to increase as the linewidth dimensions shrink.
For example, FIG. 1 illustrates a scanning electron micrograph (SEM) cross-sectional image of a test structure 100 taken near the anode end of a failed interconnect line 102 included therein, as a result of electromigration stress. The current carrying interconnect line 102 is disposed between the adjacent “extrusion monitor” lines 104a, 104b, that do not carry current. As indicated above, there are two phenomena associated with the illustrated electromigration fail. First, a metal/cap layer interface is delaminated by the high stress, with the delamination spanning across the gap between adjacent wire 104b. Second, metal extrusion of line 102 occurs and reaches the adjacent wire 104a, causing an electrical short.
Although electromigration-induced extrusion failure is not particularly prevalent in previous technologies using silicon dioxide (SiO2) and dense SiCOH (carbon doped oxide) as dielectric materials (and was generally treated as irrelevant since extrusion typically occurs long after an initial electromigration failure, defined by 20% resistance increase), this phenomenon has been more frequently observed during the evaluation of advanced technologies using ultra low-K dielectrics. A low-K dielectric material is one in which the relative dielectric constant is less than 4, while an ultra low-K dielectric is one in which the relative dielectric constant is less than 3. Accordingly, it would be desirable to be able to minimize the adverse impacts of extrusion/delamination related damage associated with the electromigration phenomenon.